Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modelling the effect of such an influential component has been widely studied from many perspectives. In this work, we proposed a new general formula for RLC interconnect circuit model in CMOS technology using fractional-order elements approach. The study is based on approximating an infinite transfer function of the CMOS circuit with a non-integer distributed RLC load to a finite number of poles. It is accurate due to the effect of adding fractional-order variables and since these variables are utilised for tuning the model to match the design regardless of its complexity. As such, Delay calculations employing our analytical model are within 0.4 absolute error of COMSOL-computed delay across a range of interconnect lengths. Furthermore, the effect of the interconnect conductivity G has been taken into account tacitly although the model included the resistance R, inductance L and capacitance C of the interconnect. A number of analyses were set up at different levels of the design to evaluate the effectiveness. First, demonstrating the significant effects of generalising parameters was gained by studying the fractionalorder impedance and propagation constant of the transmission line for a range of frequencies. Second, using MATLAB we assessed the potential of the proposed approximated model besides the exact one, which shows similarity in the fundamental features of the system such as stability and resonance. Third, the proposed approach showed that with a very small tuning reach 0.01 of the generalising parameters can achieve up to 15% improvement in the model accuracy.Index Terms-fractional calculus, modelling, on-chip interconnect, RLC interconnect, transmission line.

This paper describes an energy efficient bootstrapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. The proposed bootstrapped driver uses fewer transistors operating in the sub-threshold region, and consists of two stages. The first stage is a normal driver with PMOS and NMOS transistors that are driven by the enhancing voltage circuit (stage 2) which generates voltage levels theoretically between-VDD for pulling up to 2VDD for pulling down. Our analysis shows that the proposed implementation achieves around 20% reduction in energy consumption compared to conventional designs under a supply voltage of 0.15V VDD.

As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver's ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumed. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single-event upsets (SEU), which are known to affect DSM circuits working under low voltages. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles.