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During the development of a VLSI (Very Large Scale Integration) circuits; their internal stress due to packaging combined with local self heating becomes serious and may result in large performance variation, circuit malfunction and even chip cracking. Surface peaks thermal detection is necessary in large VLSI circuits. This paper presents a VLSI circuit thermal stress monitoring approach using surface peak thermal detector algorithm and GDS (Gradient Direction Sensors) method. The design of surface peak thermal detector algorithm (SPTDA) with flexible modularbased architecture will be presented. Several approaches were implemented to achieve a better performance for the SPTDA algorithm operation. A parallel processing strategy is used to minimize computational delay. Furthermore, a hardware-efficient factoring approach for calculating tangent and division functions required by SPTDA algorithm is used to minimize silicon space in regards of their implementation. Description of the algorithm developed for the surface peaks thermal detection and the architecture implementation results are reported and compared with finite element method (FEM) temperature computations.

Thermal monitoring is essential in integrated circuit (IC) and VLSI chip which are a multilayer structure and a stack of different materials. The increase of the internal temperature of the VLSI circuits can conduct to serious thermal and also thermo-mechanical problems. Due to aggressive technology scaling, VLSI integration density as well as power density increases drastically. Thermal phenomena research activities on micro-scale level are essential for SoC and MEMS-based applications. However, various measurement techniques are needed to understand the thermal behavior of VLSI chip. In particular, measurement techniques for surface temperature distributions of large VLSI systems are a highly challenging research topic. This paper presents an algorithm and the experimental result of silicon-die thermal monitoring method using embedded sensor cells unit. Sensor implementation results and analysis are also presented.

Silicon integrated sensors for thermomechanical stress measurement in very large scale integration (VLSI) has been studied extensively in recent years due to the increasing complexity of modern semiconductor devices. As the chip size has increased continuously to accommodate more functions in modern integrated circuits (IC) technology, the stress induced in it from packaging combined with self-heating becomes serious and may result in the device degradation, circuit malfunction, and even chip cracking. Therefore, for large VLSI devices safe operation, it is necessary to construct in situ thermomechanical stress sensors to control the spatial induced peak stress. In this article, a practical approach to the application of a gradient direction sensor (GDS) for thermomechanical stress prediction in microelectronic packaging is presented. The GDS method has been studied and analyzed for its applicability as inverse engineering problem that is capable to detect the thermomechanical stress. This study uses a thermal heat sources emplacement approach to estimate and predict stress of wafer scale integration (WSI) chip junction. Hence, the geometrical coordinates of the investigated source can be obtained by applying the gradient direction sensors. Then finite element method will be used to build models to validate thermal peaks prediction by GDS method. This way, the possibilities to minimize the thermal peaks in the critical surface areas for ball grid array packaged WSI devices will be explored. Furthermore, in microelectronic, one of the primary roles of IC packaging is to provide structural stability for the VLSI chip. Hence, several considerations have guided our study for a judicious placement of different sensors. That will enable us to establish the most homogeneous thermomechanical cartography. Subsequently, other alternatives for heat sources placement or distribution that are capable in reducing the level of thermomechanical stress will be developed.

Abstract-Due to the restriction of the number of probes that a patient can tolerate and the inaccurate information provided by the invasive temperature measurements, which provide information only at discrete points, a mathematical model simulation is more effective to help physicians in planning their thermal treatment doses. This simulation will maximize therapeutic effects while minimizing side effects. Prior to the treatment, it will provide a precise idea of the predicted reaction depending on selected doses; so new treatment strategies can be proposed and evaluated.To simulate cerebral circulation [1], we divide the fluid and matter constituents within the human head into several interacting subunits, so called compartments. Four main characteristics of the analyses of the brain model are fluid dynamics analysis, mechanical analysis, laser beam and heat transfer.The objective of this study is to simulate the Laser Interstitial Thermal Therapy in Treatment (LITT) of brain tumors including all four characteristics described above. The thermal effect of the laser during coagulation lasts around one second and its temperature is between 50 0C and 90 0C. LITT has the following results; the desiccation and retraction of the tissue to destroy tumor phenomena.Index Terms-Laser interstitial thermal therapy, thermal damage, brain cancer, bioheat transfer simulation.