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Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Therefore, this paper presents a comparative study of CMOS version and CNFET version of Operational amplifier at 32-nm technology nodes. The performance of CNFET based amplifier has been thoroughly investigated in terms of its input resistance, output resistance and AC gain. This study shows that there is considerable improvement in the above feature of amplifier using CNFET. It is founded that CNFET based amplifier have 9 times AC gain, 100 times input résistance and output resistance decrease by 9 times compared to MOSFET based amplifier at 32-nm technology node. Furthermore, comparison between two technologies for same gain bandwidth product (GBP) has also been presented.

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.

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Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selectingVthandTOXis much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage inION/IOFFratio for the same drive current.