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The Class-EM power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-EM PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonicbalance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.

This paper presents a generalized analysis of the Class-E power amplifier (PA) with a shunt capacitance and a shunt filter, leading to a revelation of a unique design flexibility that can be exploited either to extend the maximum operating frequency of the PA or to allow the use of larger active devices with higher power handling capability. The proposed PA fulfills zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) conditions, resulting in a theoretical dc-to-RF efficiency of 100%. Explicit design equations for the load-network parameters are derived, and the analytical results are confirmed by harmonic-balance simulations. Two PA prototypes were constructed with one designed at low frequency and the other at high frequency. The first PA, which employs a MOSFET and a lumped-element load-network, delivered a peak drain efficiency (DE) of 93.3% and a peak output power of 37 dBm at 1 MHz. The second PA, which employs a GaN HEMT and a transmissionline (TL) load-network to provide the drain of the transistor with the required load impedances at the fundamental frequency as well as even and odd harmonic frequencies, delivered a peak DE of 90.2% and a peak output power of 39.8 dBm at 1.37 GHz.

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{ 1 moise.safari, 2 saikat.maity, 3 christian.friesicke, 4