In this paper, we describe a programmable CAVLC decoder implemented with a video parsing coprocessor. The video parsing coprocessor is a VLlW processor that issues multiple instructions and supports condition-controlled instructions to efficiently program control intensive algorithms and customized instructions for bit operations and table matching. The complexity of the parsing coprocessor is 92 Kgates logic circuits with 7 KB SRAM and its operating frequency is 200 MHz when synthesized with a 130 nm CMOS technology. The CAVLC decoder, when operated at 192 MHz, can decode a bitstream at the rate of 40 Mbps, which corresponds to the level 4.1 of H.264/AVC full HD 1080p.
Abstract:We propose a flexible DMA subsystem suitable for multicore systems, in which DMA set-up routines are separated from DMA requesting threads and DMA completion flags can quickly be checked by DMA synchronizing threads. We will briefly describe its architecture and implementation. By using a multi-core DSP system with the proposed DMA subsystem, we implemented an H.264/AVC software decoder that can decode D1 30 frames per second when the system operating clock frequency is about 265 MHz, assuming that all cores are operated at the same system clock frequency. With experimental results for the H.264 decoder, we confirmed its flexibility and performance improvement.
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