The discovery of ferroelectric doped HfO 2 enabled the emergence of scalable and CMOS-compatible ferroelectric field-effect transistor (FeFET) technology which has the potential to meet the growing need for fast, low-power, low-cost, and high-density nonvolatile memory, and neuromorphic devices. Although HfO 2 FeFETs have been widely studied in the past few years, their fundamental switching speed is yet to be explored. Importantly, the shortest polarization time demonstrated to date in HfO 2 -based FeFET was ∼10 ns. Here, we report that a single subnanosecond pulse can fully switch HfO 2based FeFET. We also study the polarization switching kinetics across 11 orders of magnitude in time (300 ps to 8 s) and find a remarkably steep time-voltage relation, which is captured by the classical nucleation theory across this wide range of pulse widths. These results demonstrate the high-speed capabilities of FeFETs and help better understand their fundamental polarization switching speed limits and switching kinetics.

Recently, nonvolatile resistive switching memory effects have been actively studied in two-dimensional (2D) transition metal dichalcogenides and boron nitrides to advance future memory and neuromorphic computing applications. Here, we report on radiofrequency (RF) switches utilizing hexagonal boron nitride (h-BN) memristors that afford operation in the millimeter-wave (mmWave) range. Notably, silver (Ag) electrodes to h-BN offer outstanding nonvolatile bipolar resistive switching characteristics with a high ON/OFF switching ratio of 1011 and low switching voltage below 0.34 V. In addition, the switch exhibits a low insertion loss of 0.50 dB and high isolation of 23 dB across the D-band spectrum (110 to 170 GHz). Furthermore, the S 21 insertion loss can be tuned through five orders of current compliance magnitude, which increases the application prospects for atomic switches. These results can enable the switch to become a key component for future reconfigurable wireless and 6G communication systems.

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.