No abstract

Wafer level package (WLP) is one of the fastest growing segments in the semiconductor packaging industries. Low costs, small sizes, and the ease of logistics make WLP a main-stream packaging solution for a single chip. However, different from conventional packages, WLP has no final test (FT) and only relies on wafer level probing for functional test, which may induce the trouble that once wafer probing map shifts, the functionally failed dice will be shipped as good ones and result in huge economic compensations. In such situation, based on manufacturing experiences and actual experimental data, this paper provided preventive guidelines and detecting solutions to eliminate the impact from wafer probing shifts.

& CO CLUSIO SAs Low-K materials become a primary development emphasis and are used at advanced technologies in semiconductor industry, it is observed that chip crack and delamination are the commonly seen failure which may lead to reliability failure. This paper introduces a general test structure and test methodology for mechanical integrity in CPI (Chip Package Interaction) reliability qualification. To improve CPI reliability of ULK/ Low-K devices, the major challenge, chip crack/ delamination is discussed. Two sandwich structures are recommended as the feasible and practical test methodology to evaluate mechanical integrity of Low-K stacks. We performed wafer saw experiment to find failure modes and recommended actions taken by both foundry and assembly site. A package level simulation by FEA analysis successfully proved the thinner chip can effectively prevent and withstand crack propagation. We also present a wafer level reliability evaluation method which is an informative evaluation approach to facilitate process optimization. In summary, CPI's importance and necessity are highlighted throughout both wafer manufacturer and assembly house. It requires great efforts and close cooperation from both sides for a robust CPI design and process.