There exist a number of mathematical procedures for designing discrete-time compensators. However, the digital implementation of these designs, with a microprocessor for example, has not received nearly as thorough an investigation. The finite-precision nature of the digital hardware makes it necessary to choose a computational structure that will perform adequately with regard to the initial objectives of the design. This paper describes a procedure for estimating the required fixed-point coefficient wordlength for any given computational structure for the implementation of a singleinput single output LQG design. The results are compared to the actual number of bits necessary to achieve a specified performance index.* This work was performed in part at the MIT Laboratory for Information and Decision Systems with support provided by NASA Ames under grant NGL-22-009-124 and in part at the Charles Stark Draper Laboratory.