This study examines the use of Unified Power Quality Conditioner (UPQC) to mitigate the power quality problems existed in the grid and the harmonics penetrated by the non-linear loads. The UPQC is supported by the Photovoltaic (PV) and Battery Energy Storage System (BESS) in this work. Generally, the PV system supplies the active power to the load. However, if the PV is unable to supply the power then the BESS activates and provides power especially during the longer-term voltage interruption. The standalone PV-UPQC system is less reliable compared to a hybrid PV-BESS system because of its instability and high environment-dependency. Therefore, BESS will improve the voltage support capability continuously in the longer-term, reduce the complexity of the DC-link voltage regulation algorithm, and keep producing clean energy. The phase synchronization operation of the UPQC controller is directed by a self-tuning filter (STF) integrated with the unit vector generator (UVG) technique. Implementation of STF will make sure the UPQC can successfully operate under unbalanced and distorted grid voltage conditions. Thus, the requirement of a phase-locked loop (PLL) is omitted and the STF-UVG is utilized to produce the synchronization phases for the series and shunt active power filter (APF) compensator in UPQC controller. Finally, the proposed STF-UVG method is compared with the conventional synchronous references frame (SRF-PLL) method based UPQC to show the significance of the proposed technique. Several case studies are further considered to validate the study in MATLAB-Simulink software.INDEX TERMS Battery energy storage system (BESS), power quality, self-tuning filter (STF), solar photovoltaic (PV), unified power quality conditioner (UPQC).

<p>Nowadays, a distribution network is operating in a stressful manner because of a complex voltage disturbance stirred by its nonlinear, intensified, sensitive and complex loading condition with vast proliferation of electronic equipment required for the integration of renewable energy. A distribution network that mostly inflicted by the complex voltage disturbance can be referred to as the merge of stationary voltage disturbances with a short duration voltage disturbance under a nonlinear loading condition. Therefore, the dynamic voltage restorer (DVR) integrating with the battery bank will have enough energy storage to overcome long and deep complex voltage disturbance that occurs in a distribution network installed with the photovoltaic (PV) system. The results are obtained with satisfactorily findings in compensating the complex voltage disturbance using DVR.</p>

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This paper present the design and analysis of 8-bit Smith Waterman (SW) based DNA sequence alignment accelerator's core on ASIC design flow. The objective of the project is to construct and analyse the core module that can perform the Smith Waterman algorithm's operations, which are comparing, scoring and back tracing, using the technique used in [1,2] on ASIC design flow. Nowadays, the DNA and protein databases are increasing rapidly and these add new challenges to the current computing resources. New techniques, algorithms, designs, hardware and software that can maximize the computational speed, minimize the power and energy consumption, and boost the throughput need to be developed in order to meet the current and future requirements. In DNA sequence alignment process, the DNA sequences are compared using different alignment requirement techniques such as global alignment, local alignment, motif alignment and multiple sequence alignment. Moreover, there are several algorithms used to perform the sequence alignment process such as NeedlemanWunch algorithm, Smith Waterman algorithm, FASTA, BLAST and so on. For this paper, the focus is on local alignment using Smith Waterman algorithm. The design was modelled using Verilog and the functionality was verified using Xilinx and VCS. The RTL codes was mapped and synthesized to technology based logics using Design Compiler (DC). The core's layout was implemented using Place and Route tool, IC Compiler (ICC).Based on the results, the core design area was 2108.937620 um 2 .The maximum time constraints were 6.85 ns and 6.93 ns in ICC and PT. The minimum time constraints were 0.28 ns and 0.30 ns in ICC and PT respectively. In conclusion, the design had been successfully implemented on ASIC design flow. Moreover, the results showed that the design can be further optimized to work at faster speeds.

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