Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.