This research presents architecture of Ultra Low Power (ULP) Micro Energy Harvester (MEH) using Radio Frequency (RF) signal as an input. RF has many advantages compared to other ambient sources because it is not affected by changes of weather or time, does not require heat or wind exposure and it can be moved randomly within the bound of the transmission source. When RF is used as the sole input, the designer needs to consider impedance matching as the most important element so that the antenna can transfer maximum power. The existing energy harvesters apply conjugate matching network as the current solution. However, this method causes some difficulties since the solution requires consideration of both voltage boosting and conjugate matching network simultaneously. To solve this problem, we propose ULP Radio Frequency Micro Energy Harvester (RFMEH) that will utilize a control loop as voltage boosting adjuster and network tuner to achieve maximum power transfer and minimum power reflection. The proposed architecture will also improve the RF-DC conversion efficiency and the sensitivity of the system. This is achieved using an efficient rectification scheme to convert RF to DC, DC-DC boost converter to increase the dc output voltage, adaptive control circuit to adjust the switching timing of boost converter, voltage limiter and regulator to produce the best output voltage. The proposed ULP RFMEH architecture will be designed and simulated using PSPICE software, Verilog coding using Mentor Graphics and functional verification using FPGA board (FPGA) before being implemented in CMOS 0.13 µm process technology. The proposed architecture will deliver approximately 2.45 V of output voltage from low input power level (-20 dBm) with an efficiency of more than 60%. This design will minimize the power consumption as compared to previous achievements and it can be applied in supplying power for health care monitoring systems or micro biomedical applications.

This research work presents a novel architecture of an Ultra-Low-Power (ULP) based Hybrid Energy Harvester (HEH) consisting of multiple input sources such as kinetic, thermal and solar energy, harvested from passive human power. Having multiple ambient sources mitigates limitations caused by single sources especially for bodily-worn applications; however, this results in impedance mismatch among the different integrated sources. To overcome this limitation, the proposed ULP-HEH will use one power management unit with Maximum Power Point Tracking (MPPT) algorithm and impedance matching considerations to efficiently manage and combine power harvested from all three sources to achieve ULP consumptions. Among other crucial sub-modules of the ULP-HEH are its Asynchronous Finite State Machine (AFSM) cum resource sharing arbiter to prioritize and share energy sources for overall power reduction, an efficient rectification scheme for the piezoelectric input, an adaptive feedback for ULP conditioning, Zero-Current Switching (ZCS) for semi-lossless switching, a self-start circuit for low ambient startup, a Boost converter, a Buck regulator, a fuzzy-based micro-battery charger and a de-multiplexer to switch between harvesting or charging capabilities. All of which are implemented for maximum output extraction and minimal losses. This ULP-HEH will be developed in PSPICE software, Verilog coding under Mentor Graphics environment and later to be verified using Field Programmable Gate Array (FPGA) board before the final layout implementation in CMOS 0.13-µm process technology. This battery-less ULP-HEH is expected to deliver 3.0-5.0V of regulated voltage output from low ambient sources of 35 mV at startup. An efficiency of 90% with an output power of 650 µm is expected when all sources are summed. Also, this ULP-HEH is aimed at reducing power consumption to at least twice (<70 µW) of conventional approaches. The proposed ULP-HEH can be used for ULP bodily-worn electrical gadgets, wearable biomedical devices or to charge micro-batteries for portable electronic devices

This paper aims to develop and design the architecture of Low Power Hybrid Energy Harvester (LPHEH) using the hybrid input of solar and thermal that can be harvested for self-powered laptop or notebook. This research will focus on the development of the high performance boost power converter to power up any laptop or notebook and design power management system of the hybrid input of solar and waste heat that has been released. The main function of the boost converter is to generate a sufficient DC power supply for laptop or notebook. The second stage focuses on investigation, design and development of the architecture to convert the solar and waste heat energy to reusable energy. The solar energy harvesting elements such as solar panels and energy storage components are used and to be matched to each other with sufficient energy required to increase the energy harvesting efficiency. The proposed design performances will be described using PSPICE software simulation and experimental results. The final stage is to integrate the first stage and second stage, power management module and charge controller module. Then, the developed LPHEH will be simulated, synthesis using Mentor Graphics and coding using Verilog and then download the LPHEH modules into FPGA board for real time verification. The layout architecture of LPHEH will be tested and analyzed using CALIBRE tools from Mentor Graphics. The expected result from this LPHEH is to get 12 V to 20 V of the regulated output voltage from minimum input voltage sources range from 5 V to 12 V with efficiency more than 90%.