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Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures.

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Due to the increase in the number of vehicles day by day, traffic congestions and traffic jams are very common. One method to overcome the traffic problem is to develop an intelligent traffic control system which is based on the measurement of traffic density on the road using real time video and image processing techniques. The theme is to control the traffic by determining the traffic density on each side of the road and control the traffic signal intelligently by using the density information. This paper presents the algorithm to determine the number of vehicles on the road. The density counting algorithm works by comparing the real time frame of live video by the reference image and by searching vehicles only in the region of interest (i.e., road area). The computed vehicle density can be compared with other direction of the traffic in order to control the traffic signal smartly.