The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool. Keywords:Conditional INTRODUCTIONThe Complementary Metal Oxide Semiconductor (CMOS) technology becomes a major part in advanced process of Very Large Scale Integration (VLSI) applications. It increases the leakage current, shows improvement in scaling and enhances the sensitivity which makes the factor fluctuations as barriers of scaling technology in CMOS. As per the improvement of wireless portable systems with the speed of microprocessors and less budget on power the VLSI circuit is rapidly integrated. In the transistor technology, the supply of power simultaneously scaled down and achieves less consumption of power and faster. As well as the threshold voltage is lesser in the similar proportionate. The threshold voltage scaling in exponential provides less immune of noise and improves the sub threshold leakage current in the transistor. In the dynamic node, the dynamic capacitance and supply voltage of domino logic reduces the storage of charges. As per the synchronized factor, the technology scaling is deceased by the substantially of domino gate immunity noise. The high leakage makes the system as difficult due to parallel process of the path evaluation.The wide fan-in domino has become difficult if there is high immunity of noise and leakage. It happens due to the parallel process and the charge leakage from the node of pre-charge. In the dynamic node, the keeper transistor is prevented by employing the undesired discharging because of charge sharing and leakage current of pull down network. It processes during the phase of evaluation and progresses the robustness by upsizing between the network evaluation and transistor. Also it enhances the delay of the circuit, shows improvement in power consumption and performance. Therefore, the delay and power are considered by compromising the leakage current, upsizing the keeper and noise improvement. The keeper ratio (K) is defined as the ratio of the product of electron mobility and aspect ratio of the keeper transistor to the product of hole mobility and aspect ratio of the evaluation network.

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There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

Due to the tremendous increase in the call of handheld devices like mobile, iPods and tablets; certain applications like space and biomedical, it is necessary to have low power consuming digital systems. As a crucial part in digital systems,Static Random Access Memory(SRAM) should consume low power since it occupies about 70% of the total chip area. As the technology is shrinking, SRAM’s leakage power in standby condition is becoming a most critical concern for the low power applications. This paper gives a study of different leakage components present in SRAM and discusses about various current reduction techniques which include Gated VDD, MTCMOS, Dual threshold and Transistor Stacking.