This paper proposes a highly efficient Time-Based Maximum-Power-Point-Tracking (TB-MPPT) integrated-circuit. Conventional TB-MPPT circuit shows unstable status (oscillation) near the Maximum Power Point (MPP), which causes the degradation of the overall power tracking efficiency. To overcome this critical issue, the proposed circuit separates the tracking operation into two periods, and it utilizes convergence range averaging technique with an adaptive perturbation step according to each control signal to accurately extract the current power level without oscillation problem. This work is fabricated in 180 nm CMOS process to demonstrate advantages of the proposed scheme. With 0.47V 12mW Photovoltaic (PV) cell, the measurement results show 94.2% of MPPT efficiency and 91.6% of power conversion efficiency (PCE). It occupies silicon chip area of 1.69 mm 2 .

A hybrid control method using a comparator and a charge control method is proposed for a single-inductor multiple-output (SIMO) DC-DC converter. SIMO DC-DC converters have the weaknesses relating to cross-regulation, as all the output channels share the energy stored in a single inductor. Although multiple control methods such as Time-Multiplexing Control (TMC) and Ordered Power Distributing Control (OPDC) have been proposed to prevent cross-regulation or to improve load capability, effective use of limited resources appears to have not yet been achieved. This paper introduces a hybrid control topology that (1) utilizes comparator-based regulations for most outputs and (2) uses a new charge control loop method for the last output to reduce cross-regulation with low hardware complexity. In addition, the proposed scheme efficiently reuses the system’s redundant energy by adaptively controlling the freewheeling switch that opens the path to the input battery to store the surplus energy resources again. The proposed SIMO DC-DC converter was designed and validated with a 0.18 μm 3.3 V CMOS process. The converter has four regulated outputs of 0.9, 1.2, 1.5, and 2.2 V, and as a result of the simulation, it was found that the cross-regulation was estimated to be 0.4 mV/mA when the output current changes by ~200 mA. In addition, estimated peak power conversion efficiency of 88.5% was achieved at a total output power of 405 mW.

Distance computation between two input vectors is a widely used computing unit in several pattern recognition, signal processing and neuromorphic applications. However, the implementation of such a functionality in conventional CMOS design requires expensive hardware and involves significant power consumption. Even power-efficient current-mode analog designs have proved to be slower and vulnerable to variations. In this paper, we propose an approximate mixed-signal design for the distance computing core by noting the fact that a vast majority of the signal processing applications involving this operation are resilient to small approximations in the distance computation. The proposed mixed-signal design is able to interface with external digital CMOS logic and simultaneously exhibit fast operating speeds. Another important feature of the proposed design is that the computing core is able to compute two variants of the distance metric, namely the (i) Euclidean distance squared (L22 norm) and (ii) Manhattan distance (L1 norm). The performance of the proposed design was evaluated on a standard K-means clustering algorithm on the “Iris flower dataset”. The results indicate a throughput of 6 ns per classification and ∼2.3× lower energy consumption in comparison to a synthesized digital CMOS design in commercial 45 nm CMOS technology.

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