In this paper, we present the newly developed intra‐panel interface targeting to replace conventional multi‐drop bus architecture with point‐to‐point differential interface. The multi‐level signaling scheme is adopted to remove separate clock and control signal lines by embedding clock information into multi‐level signal. The clock embedding scheme removes the skew problem found in previously announced intra‐panel interface, and provides lower EMI. The simple multi‐level signal detector is used to regenerate the clock signal from the data stream and does not require any sophisticated clock recovery unit in the receiver. The AiPi can be an effective solution to large size TFT LCD applications due to the reduced signal lines, lower EMI, and lower power consumption.

Emerging power-supply-on-chip applications such as on-chip DC-DC conversion, energy harvesting, and LED drivers use switching regulator ICs integrated with digital controllers. Although the resulting mixed-signal systems call for efficient system-level behavioral simulation, this remains difficult due to the fast switching and slow transients of the regulator and the high complexity of the controller. This paper presents a truly eventdriven approach for modeling and simulating such integrated power systems entirely in SystemVerilog. By modeling various switching regulator topologies as switched linear networks whose responses can be expressed as a sum of complex exponentials, ct m-1 e −at u(t), the accurate voltage/current waveforms can be captured by updating the coefficients, c, at each input or switching event. The model is applied to two examples, a power factor corrector and switched-capacitor DC-DC converter, and the results demonstrate that the proposed simulator can achieve 20~100× improvements in speed while maintaining SPICE-level accuracy in evaluating power efficiency, steady-state ripples, and power factor.

This paper presents a new type of gate driver IC that can significantly reduce the gate switching loss by leveraging high-speed and low-power operation of custom integrated circuits. The gate driver itself works as a mini bidirectional buck converter, which charges and discharges the gate terminal of a power device (e.g. IGBT) by feeding a chain of short pulses whose widths gradually increase or decrease into an LC filter. A set of circuit techniques to minimize the energy consumption in generating these pulses at the required frequency of up to 50-MHz and duty-cycle resolution of 5% is presented. A prototype IC fabricated in a 0.25-P Pm HV CMOS demonstrates 27.8-mW power consumption or equivalently 62% energy recycling while switching a 120-nC IGBT at 40-kHz and 15-V.

: High bending collapse performance (maximum resistance force and mean resistance force) of body center pillar is an important design target for vehicle safety against side impact. In this study, effect of the upper section shape and the thickness of outer reinforcement on bending collapse performance was investigated for the center pillar of a large passenger car. First, through bending collapse analyses using simple models with uniform section, an optimized center pillar upper section was chosen. Next, bending collapse performance for various models of the actual center pillar with changing the thickness of outer reinforcement were analyzed. The finally designed model showed distinctive enhancement in bending collapse performance nearly without weight increase.

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