The interface trap properties of metal/oxide/silicon field-effect transistors with high-k gate dielectrics are evaluated by the charge pumping method and related with electrical characteristics of the transistors. It is found that the gate leakage current is very sensitive to the interface traps by which the barrier height of Fowler–Nordheim tunneling is also influenced. The inversion layer mobility is greatly influenced by the charges in the gate insulator as well as by the interface traps. We propose a simple method to extract the geometrical mean value of capture cross sections of traps ranging from 7.03×10−21 to 2.22×10−22 cm2.

The channel width dependence of gate delay in 0.18-m CMOSFET has been characterized. Substantial increase of gate delay observed in the narrow channel width region is found due to channel width independent capacitance components, which is inherent to transistors. An expression for gate delay considering the channel width independent capacitance components and gate sheet resistance is derived and compared with experimental data. The minimum gate delay is shown to result from the compromise between delay components proportional to channel width and proportional to inverse of channel width. Although the channel width independent capacitance is negligible in the wide channel width region, the gate delay of the 1-m channel width ring oscillator increased more than 20% compared with the 5-m channel width ring oscillator.Index Terms-Channel width independent capacitance, gate delay, gate sheet resistance, 0.18-m CMOSFET.