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Conventional clocked line sensors generate large amounts of data when employed in high-speed short-latency machine vision applications because they read out data of all pixels at a fixed rate. For various problems such as measurement tasks, shape detection, object orientation extraction etc., a substantial fraction of the image data produced does not provide any information necessary to accomplish the function or to increase reliability or precision. One way to suppress image data redundancy is to use a self-timed data-driven sensor architecture.The optical line sensor presented here combines an asynchronous pixel circuit with on-chip precision time-stamping and a synchronous bus arbiter. The temporal resolution of this new sensor is 100ns (compared to line rates on the order of 100kHz for the fastest clocked line sensors [1][2][3][4]) and is beneficial for various high-speed machine vision applications that do not rely on conventional image data. The output data volume depends on the dynamic contents of the scene and is typically orders of magnitude lower than equivalent data output produced by clocked line sensors in this type of applications.Each pixel operates autonomously and responds with low latency to relative illumination changes by generating asynchronous events [5]. Pixels that are not stimulated do not produce outputs. The circuit combines an active continuous-time logarithmic photo-sensor with a self-timed differentiating switched-capacitor amplifier, threshold comparators and handshake logic. It generates two types of events, which represent a fractional increase or decrease in intensity that exceeds a tunable threshold. Combined with the pixel address, these events are referred to as 'address-events' (AE) [6]. The pixel is able to detect contrast changes of a few percent over a dynamic range of >120dB. The wide dynamic range arises from the logarithmic compression in the front-end photoreceptor circuit and the local (pixel intrinsic) event-based differentiation operation [5]. The 28T3C pixels measure 15µm×165µm in a standard 0.35µm CMOS process and are arranged in a 2×256 dual-line configuration with 15µm pixel pitch and 250µm line separation.Time-stamps are traditionally assigned to asynchronous addressevent data by a post-processor after arbitration of a shared communication channel, e.g. [6]. Depending on data rate and arbitration strategy, a non-deterministic variable latency affects the timing precision of the data [7-8]. The architecture presented here performs the time-stamp assignment at the pixel level. Time-stamps are combined with the corresponding address events to compose a synchronous stream of data packets. Events occurring during the same time-stamp period are interpreted as concurrent and are arbitrated in the order of their addresses. Pixel addresses and time-stamps are read out via a 3-stage pipelined synchronous bus arbiter. A single set of output data from the sensor is referred to as a 'timed addressevent' (TAE).A block diagram of the chip is shown in Fig. 28.1.1. Pixels signa...

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