The laboratory plays a vital role in the logic design learning process. Specifically, the laboratory provides an avenue by which design concepts presented in lecture may be exercise in a controlled environment, promoting student participation and feedback. As such, laboratory is intended to augment the lecture in providing both basic theory and applications of logic design. The result of this combined effort is to develop sound design techniques as well as to familiarize the student with logic devices used to implement these techniques using the latest technology. In this paper, a discussion of the usefulness of the ALTERA programmable logic development system will be presented. The system combines hardware and software to program and test digital logic circuits.

This paper presents a conceptual framework for modeling of CMOS stuck-open faults by classical stuckat faults.Stuck-open faults can be mapped one-toone onto stuck-at faults for a gate level, clock mode fault simulation. The disadvantage of this modeling is that it restricts the circuit layout to logic gates hence, an increase in chip area is expected. Such increase is acceptable when the modeling reduces the staggering fault simulation time by a large factor.