The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one of the widely used protocols for SoC designs. Out of its three different interconnect protocols: lite, stream and burst, AXI4-lite has the simplest architecture design that best suits to be used in applications where power, area and performance play a vital role. This paper briefs about using AMBA AXI4-lite bus protocol with more bus efficiency and performance in an SoC design for proper communication between various functional blocks present. The RTL is verified using UVM (Universal Verification Methodology) and various designing process is carried out using cadence tools.