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A new technique to measure the lateral diffusion distance of boron has been developed by wet-etching combined with TEM and Electron Energy Loss Spectroscopy (TEM-EELS). The position at a dopant concentration of 5×1018 cm-3 can be correctly delineated with a spatial resolution of less than 5 nm. This technique is based on the fact that the gradient of the etched surface changes discontinuously at a dopant concentration of 5×1018 cm-3. This characteristic appeared for all carrier profiles as long as the etching time was sufficiently long. Etching time optimization is needed because an incubation time exists before the etching starts and because the incubation time depends on carrier distribution. Thickness distribution after the etching is measured by TEM-EELS which enables a high spatial resolution measurement. The lateral diffusion distance at the pn junction measured by this technique was about 0.6 times of the vertical diffusion distance for 40–80 nm junctions. These results were compared with those obtained by an electrical C-V measurement, and were consistent.

This paper presents several examples of defect analyses carried out in actual VLSI failure analyses and experiments, using TEM technique, process simulation and other advanced analytical tools. New TEM techniques are also described to observe a precise location which has failed.

TEM(Transmission Electron Microscope) observation for the device failure analysis is strongly demanded to achieve high production yield and high reliability of VLSI memories with a high bit density and a. complicadd structure. We have developed a new XTEM(cross sectional TEM) sample preparation technique using FIB(Focused Ion Beam) marking [1], which makes it possible to observe a specified point on VLSI chips. Applying this technique to the analysis of retention-time-failure bits in a DRAM with trench cells, it was found that the oxygen precipitate exists near the trench bottom of the failure bit with excess node-to-substrate leakage current. After a, retention failure bit on a chip is specified with IC tester, V-shape and I-shape patterns are grooved by using the FIB, as shown in Fig.l. The Vshape pattern is used for a position monitoring during the sample thinning, while the I-shape pattern defines the location of the failure bit cell after th.e sample preparation i s completed. Monitoring the specified cell by SlM(Secondary Ion Microscope) image in FIB machine, V and I patterns were formed in the positions 2-3pm apart from the failure cell. The cell-to-mark distance of 2-3pm is necessary to avoid FIB induced damages.

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