This paper introduces a new versatile and highperformance parallel hardware engine for matrix computations. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies and employing distributed memory structures. It is designed to better utilize the on chip area for computing different types of matrix computations such as matrix power, multiplication, and inversion. The matrix power presented in this paper is proven to be two times faster than normal computations. As well, the architecture is optimized to suitably perform Least Square computations in signal processing applications. The synthesis results on FPGA platforms indicate that the proposed architecture can operate in 75 MHz for 16 bit word length and the peak attained performance is about 2400 MMAC operations with 32 concurrent MAC modules.

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A pre-computation based technique to lower the power consumption of sequential multipliers is presented. This technique also speeds up the multiplication by reducing the number of clock ticks required to complete a multiplication. The proposed technique may be applied to different sequential multiplication schemes. The benchmark data is extracted from typical DSP applications to show the efficiency of the proposed technique in the domain of DSP computations in which the low power computing is of rapidly increasing importance. The results show an average of 25% reduction in the switching activity and 30% reduction in the clock tick count, compared to sequential multipliers without this technique.

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