The article discusses an approach to organizing the interaction of nodes of spacecraft onboard data transmission networks based on wireless communication technologies. The main quality indicators and requirements for traffic control in on-board networks are formulated taking into account the peculiarities of the wireless network nodes interaction. The results of modeling various algorithms of transmission medium access control for one of the common protocols for organizing wireless networks (IEEE 802.15.4) are presented..
Using small spacecrafts for a wide range of research and applied purposes is one of the major trends in the aerospace field. Modular-network architectures implemented on the "system-on-chip" hardware platform provide required characteristics of onboard control systems. Selecting this system architecture significantly increases demands on very large-scale integration (VLSI) design efficiency and project solution quality. In this paper, we propose a new approach to VLSI high-level synthesis based on a functional-flow parallel computing model. The modified VLSI design flow uses a functional-flow parallel programming language Pythagoras, which allows describing a VLSI operation algorithm with the maximal degree of parallelism. An offered intermediate representation of VLSI architecture in the form of a control-flow graph and a data-flow graph provides an opportunity for synthesizing circuits and verifying projects on the stage of a formal description, without returning to previous hierarchical levels of the project. A set of software tools supporting new design process is developed. The proposed technology is successfully tested on the example of a digital signal processing function. Further, this technology is suggested for use in the synthesis of onboard control system components for small spacecrafts.
В современных информационных системах различных автономных технических объектов прослеживаются тенденции увеличения числа компонентов бортовой аппаратуры, это приводит к усложнению бортовой сети передачи данных. При использовании традиционных интерфейсов резко возрастает число кабельных линий и общий вес системы. Одним из вариантов решения данной проблемы может быть использование беспроводных технологий передачи данных. Использование среды общего доступа в беспроводных сетях делает их характеристики зависимыми от большого числа условий, например числа активных узлов. В работе рассматривается влияние различных алгоритмов управления доступом к среде на технические характеристики системы. Оценивается возможность применения отдельных алгоритмов для построения бортовых беспроводных сетей. На основе анализа качественных показателей выделяются два наиболее перспективных и проводится их моделирование в среде OMNeT++. Показано изменение их характеристик при росте числа активных узлов. Сделаны выводы о возможности использования в беспроводных сетях автономных объектов. Результаты моделирования отражают преимущества отдельных алгоритмов при разном количестве узлов. Это позволяет сделать вывод о перспективности дальнейших исследований с целью построения комбинированного алгоритма, который бы сочетал лучшие свойства каждого алгоритма. Ключевые слова: беспроводные бортовые сети, методы управления доступом к среде, TDMA, CSMA/CA, имитационное моделирование, OMNeT++
The problems and solutions in the field of ensuring architectural independence and implementation of digital integrated circuits end-to-end design processes are considered. The paper focuses on the need to find a solution to the problem of program portability during the development of integrated circuits. A review of the main software and tools used to design digital circuits (Verilog, System-C, Handel-C, Lava, Hydra, Wired, COLAMO, Chisel and etc.) is presented. The method and language of parallel programming for functional flow synthesis of design solutions PIFAGOR is presented. The example of the source and generated code in the PIFAGOR and Verilog languages is given. During the method implementation, the tasks of reducing parallelism and estimating the occupied resources were highlighted. The main feature of the developed method is the introduction of the additional layer (HDL graph) into the synthesis process. Algorithms for the parallelism reduction have been developed. This method is demonstrated on the example of parallelism reduction while going to the FPGA platform solving the problem of calculating a 4-point FFT (Fast Fourier Transform). As part of the solution of this task, an assessment of memory resources and an assessment of computing resources were carried out. The results of software tools development for design support including the parallelism reduction preprocessor and resource estimation preprocessor and practical VLSI projects are presented.
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