Thin films of Sr x Ba 1−x Nb 2 O 6 (SBN:x) are particularly attractive for their potential use as low voltage electro-optic waveguides. This potential application in integrated optics requires the control of the (001) oriented SBN growth on a conductive substrate. We have prepared (001) SBN:x thin films on Pt coated MgO substrates by using sputtering techniques and rapid thermal annealing. The dielectric non linearity of the SBN:x films is investigated as a function of the Sr content (x = 50, 60, or 70%) and annealing conditions. It is maximum at the ferroelectric-paraelectric transition temperature of the film (175 • C, 116 • C and 40 • C for x = 50, 60, and 70% respectively). At room temperature and with a Sr content of 60%, the relative variation of the dielectric permittivity [ε(0)-ε(E)]/ε(0) is found equal to 46% for an applied electric field E = 43 kV/cm. Due to a transition temperature closer to room temperature, a dielectric non linearity of higher value, less sensitive to temperature and little affected by hysteresis, is expected from films of higher Sr content.

A technological break based on Wafer Level Package started in 2002, consists in only stacking Known Good Reconstructed Wafer (what Freescale named: RCP and Infineon named eWLB) instead of standard wafers. This approach allows to have a very good yield, on the contrary of the W2W with TSV technologies. Several applications will be presented on the medical area, industrial area and smart card area.

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130 °C +175 °C, 40000g), and is fully qualified by all worldwide most important Space Agencies, for Defence applications and Harsh environment. A technological break started in 2002 ; it consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules. The Z pitch is 100 μm and the X Y size is given by the size of the larger die plus 100 μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Freescale (RCP technique up to 300mm), then Infineon and Nanium (ex Infineon/Quimoda) and now about ten companies are developing this 2-D approach:- Stacking and gluing of KGRW 1, 2, 3..., n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100 μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20 μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation This approach allows to use standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to obtain an excellent yield. A development agreement has been signed with a semiconductors manufacturer. Smart card application- A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice within a cavity of 550 μm inside the 800 μm SIM card. Medical applications will be presented:- Micro modulator with 5 ASICs within a 3 mm diameter tube,- Prototypes for the major US pacemaker manufacturer (Medtronic) and one European pacemaker manufacturer (Sorin/Ela Medical). A full pacemaker module of 0,5 cm3 (16 times smaller than the standard pacemaker: 8 cm3) will be shown- Micro camera for Hard X-Ray for Philips Medical (DE). Industrial applications- Abandoned sensors for Airbus and industrial areas. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows to stack Good wafer at the reverse what is impossible with the wafer to wafer approach.