A new generation of high-efficiency power devices is being developed using wide bandgap (WBG) semiconductors, like GaN and SiC, which are emerging as attractive alternatives to silicon. The recent interest in GaN has been piqued by its excellent material characteristics, including its high critical electric field, high saturation velocity, high electron mobility, and outstanding thermal stability. Therefore, the superior performance is represented by GaN-based high electron mobility transistor (HEMT) devices. They can perform at higher currents, voltages, temperatures, and frequencies, making them suitable devices for the next generation of high-efficiency power converter applications, including electric vehicles, phone chargers, renewable energy, and data centers. Thus, this review article will provide a basic overview of the various technological and scientific elements of the current GaN HEMTs technology. First, the present advancements in the GaN market and its primary application areas are briefly summarized. After that, the GaN is compared with other devices, and the GaN HEMT device’s operational material properties with different heterostructures are discussed. Then, the normally-off GaN HEMT technology with their different types are considered, especially on the recessed gate metal insulator semiconductor high electron mobility transistor (MISHEMT) and p-GaN. Hereafter, this review also discusses the reliability concerns of the GaN HEMT which are caused by trap effects like a drain, gate lag, and current collapse with numerous types of degradation. Eventually, the breakdown voltage of the GaN HEMT with some challenges has been studied.

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Purpose The purpose of this study is to demonstrate a pseudomorphic High Electron Mobility Transistor (pHEMT) cutoff frequency (fT) and maximum oscillation frequency (fmax) are determined by the role of its gate length (Lg). Theoretically, to obtain an Lg of 1 µm, the gate’s resist opening must be 1 µm wide. However, after the coat-expose-develop (C-E-D) process, the Lg became 13% larger after metal evaporation. This enlargement is due to both resist thickness and its profile. Design/methodology/approach This research aims to optimize the 1-µm Lg InGaAs-InAlAs pHEMT C-E-D process, where the diluted AZ®nLOF™ 2070 resist with AZ® EBR solvent technique has been used to solve the Lg enlargement problem. The dilution theoretically allows the changing of a resist thickness to different film thickness using the same coating parameters. Here, for getting a new resist, which is simply called AZ 0.5 µm, the experiment’s important parameters such as the coater’s spin speed of 3,000 rpm and soft bake at 110°C for 5 min are executed. Findings The newly mixed AZ 0.5 µm resist has presented a high resolution and undercut profile rather than standard AZ 1 µm resist. Hence, the Lg metallization after using AZ 0.5 µm optimized process showed better results than AZ 1 µm which used the standard process. Originality/value The outcome of the optimization has reached that it is possible to get a nearly sub-µm range gate’s opening using a diluted resist, and at the same time retaining a high resolution and undercut profile.