No abstract

Dynamic voltage and frequency scaling (DVFS) is heavily used for power management in real-time environments. Although the schemes leveraging DVFS provide significant power reduction, adverse effects on chip reliability are possible. Alternate increase and decrease in operating voltage and frequency leads to thermal cycling. Increasing transistor packing density leads to a larger range of possible operating temperatures, exacerbating the thermal cycling problem. Also, the chip reliability quantification process does not include and represent the effects of small scale thermal cycles. A good number of in-field chip failures are attributed to the consequences of these. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work develops an integrated processor thermal and performance management technique centered on novel polynomial time scheduling algorithms that lead to lowering of thermal cycles in soft real time environments. Our technique leverages application awareness and runtime monitoring for improving chip lifetime, while achieving considerable energy savings. We show that a significant reduction in thermal cycles and peaks is possible, leading to longer chip life expectations.

Dynamic Binary Optimization and dynamic compilation based schemes are widely employed for runtime program optimization. They are effective in specific program scenarios, but their scope of applicability is limited by the associated runtime overhead. Their capabilities can be exploited well with the knowledge of program parameters and execution conditions. These high level structures affect the runtime optimization decisions, thereby reducing the overhead in rediscovering them. In the current program flow process, the binary executable files are devoid of this program high-level structure. Such structures exist at earlier stages, i.e., at higher level program in the compiler front end generated parse and attributed abstract syntax trees, and data structures generated in the compiler back end for optimization, i.e. a call graph. However, the information is discarded at the final code generation stage.In this paper, we develop a framework that automatically captures attributes of program structure, which are carried forward through static compilation. They are used to make the runtime optimization process faster and lightweight in nature. We also develop a novel Runtime Management Module (RMM) to control the program execution process and reoptimize the code to better suit the current execution conditions, as needed. Our metadata extraction techniques coupled with the effectiveness of RMM results into significant performance gains during execution of diverse benchmarks from SPEC and Splash 2 benchmark suites.

Existing schemes for dynamic voltage and frequency scaling (DVFS) do not account for the intertask thermal cycles. The chip reliability testing process usually also is not inclusive of test cases quantifying the chip reliability in the presence of small scale thermal cycles. However, a good number of in-field chip failures are attributed to the consequences of thermal cycles. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work focuses on developing an integrated processor thermal and performance management system centered on novel polynomial time scheduling algorithms that achieve minimal thermal cycle guarantees in soft real time environments. Our scheme leverages application awareness and runtime monitoring for improving the lifetime of the chip, while achieving considerable energy savings. Our scheme shows a significant reduction in thermal cycles and peaks, leading to longer chip life expectations. Our results indicate a 10 fold increase in the expected chip lifetime and 50% energy savings compared to operation at the rated maximum voltage and frequency.