This paper presents a new signature monitoring technique, CFCSS (Control Flow Checking by Software Signatures); CFCSS is a pure software method that checks the control flow of a program using assigned signatures. An algorithm assigns a unique signature to each node in the program graph and adds instructions for error detection. Signatures are embedded in the program during compilation time using the constant field of the instructions and compared with run-time signatures when the program is executed. Another algorithm reduces the code size and execution time overhead caused by checking instructions in CFCSS. A "branching fault injection experiment" was performed with benchmark programs. Without CFCSS, an average of 33.7% of the injected branching faults produced undetected incorrect outputs; however, with CFCSS, only 3.1% of branching faults produced undetected incorrect outputs. Thus it is possible to increase error detection coverage for control flow errors by an order of magnitude using CFCSS. The distinctive advantage of CFCSS over previous signature monitoring techniques is that CFCSS is a pure software method, i.e., it needs no dedicated hardware such as a watchdog processor for control flow checking. A watchdog task in multitasking environment also needs no extra hardware, but the advantage of CFCSS over a watchdog task is that CFCSS can be used even when the operating system does not support multitasking.

This paper proposes a pure software technique, Error Detection by Duplicated Instructions (EDDI), for detecting errors during normal system operation. Compared to other error detection techniques that use hardware redundancy, our method does not require any hardware modifications to add error detection capability to the original system. In EDDI, we duplicate instructions during compilation and use different registers and variables for the new instructions. Especially for the fault in the code segment of memory, we have derived formulas to estimate the error detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. We applied our technique to eight benchmark programs and estimated the error detection coverage. Then, we verified the estimates by simulations, in which a fault injector forced a bit flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault injection experiments, we show that EDDI can provide over 98% fault coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware system but they need dependability in the computer system. The Control Flow Checking by Software Signatures (CFCSS) technique can be used with EDDI to increase the fault coverage. In order to reduce the performance overhead, our technique schedules the instructions that are added for detecting errors such that Instruction-Level Parallelism (ILP) is maximized. We have showed that the execution time overhead in a 4-way super-scalar processor is less than the execution time overhead in the processors that can issue 2 instructions in one cycle.

Errors in computing systems can cause abnormal behavior and degrade data integrity and system availability. Errors should be avoided especially in embedded systems for critical applications. However, as the trend in VLSI technologies has been towards smaller feature sizes, lower supply voltages, and higher frequencies, there is a growing concern about temporary errors as well as permanent errors in embedded systems; thus, it is very essential to detect those errors. Software Implemented Hardware Fault Tolerance (SIHFT) is a low-cost alternative to hardware fault tolerance techniques for embedded processors: it does not require any hardware modification of Commercial Off-The-Shelf (COTS) processors. ED 4 I is a SIHFT technique that detects both permanent and temporary errors by executing two "different" programs (with the same functionality) and comparing their outputs. ED 4 I maps each number, x, in the original program into a new number x′, and then transforms the program so that it operates on the new numbers so that the results can be mapped backwards for comparison with the results of the original program. The mapping in the transformation of ED 4 I

The Advanced Space Computing and Autonomy Testbed on the ARGOS Satellite provides the first direct, on orbit comparison of a modern radiation hardened 32 bit processor with a similar COTS processor. This investigation was motivated by the need for higher capability computers for space flight use than could be met with available radiation hardened components. The use of COTS devices for space applications has been suggested to accelerate the development cycle and produce cost effective systems. Software-implemented corrections of radiationinduced SEUs (SIHFT) can provide low-cost solutions for enhancing the reliability of these systems. We have flown two 32-bit single board computers (SBCs) onboard the ARGOS spacecraft. One is full COTS, while the other is RAD-hard. The COTS board has an order of magnitude higher computational throughput than the RAD-hard board, offseting the performance overhead of the SIHFT techniques used on the COTS board while consuming less power.

In Algorithm-based fault tolerance (ABFT)