With the progress of semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of fabricated chips. The amount of delay degradation is known to be circuit and workload dependent, but previous evaluations are based on simulations, and delay degradation measurement of real circuit under realistic workload has not been reported yet. This paper proposes real circuit delay measurement method, which achieves enough accuracy to measure circuit and workload dependent delay degradation. In the proposed method, onchip oscillator supplies fine resolution variable frequency clock to internal circuit. Internal circuit execute test pattern to activate critical paths at various frequency and determine the maximum frequency at which correct results can be obtained. The maximum frequency corresponds to the delay of the critical paths activated by the test pattern. Clock multiplication improves delay resolution, and repetitive measurement reduces measurement error caused by time dependent random delay variation. The proposed method has been implemented on a 65 nm low power process test chip. Variable frequency oscillator utilizes only standard cells and is designed with automatic layout flow without any timing tuning. The area overhead of the proposed method is 0.09% of the total random logic. The evaluation result show that 0.18% average measurement accuracy has been achieved.

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With the progress of the semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of the fabricated chips. The amount of the delay degradation is known to be circuit and workload dependent, but previous evaluations are based on the simulations, and the delay degradation measurement of real circuit under realistic workload has not been reported yet. The authors have already proposed a real circuit delay measurement method, which can achieve enough accuracy to measure the circuit and workload dependent delay degradation. This paper reports the measurement results utilizing the proposed method. The measured degradation is approximated by the log and the power-law functions. Methods to correct the environmental condition variation effect, and to mitigate the approximation inaccuracy caused by the random delay variation has been developed. The measurement results show large degradation amount variation, which can be attributed to the dependence on the circuits and the workloads. On the other hand, correlation of the degradation amount between different chips is rather weak. This leads to the conclusion that the temperature dependence and the random variation of the degradation amount between different transistors have large effect on the degradation amount variation.