No abstract

As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Process Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask coOptimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO's Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorporating this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements.