Hsiao and extended Hamming parity-check matrices can be used to define systematic linear block codes for Single Error Correction-Double Error Detection (SEC-DED). Their fixed code word parity enables the construction of low density parity-check matrices and fast hardware implementations. Fixed code word parity is enabled by an all-one row in extended Hamming paritycheck matrices or by the constraint that the modulo-2 sum of all rows is equal to the all-zero vector in Hsiao paritycheck matrices. In this paper, we show that these two constraints are particular instantiations of a more general constraint which involves an arbitrary number of rows in the parity-check matrix. As a consequence, sparser paritycheck matrices with faster hardware implementations can be found. Moreover, special instantiations of these matrices enable the detection of all triple-bit and quadruplebit burst errors.

Abstract. Power savings are nowadays crucial in embedded system contexts such as Wireless Sensor Networks (WSN) in order to increase the lifetime of sensor nodes. In this paper, we propose a new hardware structure called "Power-On Controller" (POC) for applying advanced control strategies for the "idle to active" node state transition. The proposed POC allows an optimization of power control by using event accumulation and spatial selectivity mechanisms. These new features allow to reduce the dynamic power consumption of roughly 60% compared to state-of-the-art power management solutions for a typical WSN applicative context, without altering the quality of service. The POC structure can be easily integrated in any sensor node based on system-on-chip design.