Among the assorted logic styles used in fostering the integrated circuits, the domino logic styles offers higher speed and smaller transistor count as compared to the static cmos circuits. However the domino logic suffers from lower noise immunity and higher power dissipation due to the problem of charge sharing and sub-threshold leakage currents. In this paper some of the earlier proposed techniques to reduce the power consumption of the domino circuits like Dual threshold voltage (DTV) and Dual threshold voltage-voltage scaling(DTVS) have been analyzed. A novel stacked transistors Dual threshold voltage (ST-DTV) approach which deploys DTV technique with stacked transistors together with a voltage regulated static keeper is analyzed to abate the total power dissipation of the circuit together with a better Power delay product (PDP). The ST-DTV design is tested on a 3input OR gate and a 4x1 multiplexer at 90nm technology on multiple voltages and frequencies. Tanner tool EDA v13.0 is used for simulation.

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Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The core of this paper consist of the introduction of a novel and high performance design of an 8x8 multiplier using ancient Indian mathematics called Vedas. This paper presents four different designs which includes 8x8 Vedic multiplier and 8x8 array multiplier implementation using CMOS and Hybrid PTL/ CMOS logic style and finally proved that Hybrid PTL(Pass Transistor Logic)/CMOS design of Vedic Multiplier is the best among all these implementations .The multiplier and the adder-subtractor units used for the implementation of Vedic multiplier are adopted from ancient methodology of India mathematics called as Vedas. The use of Vedas not only abates the carry propagation taking place from LSB to MSB but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power among these four multipliers. The functionality of all the four designs and there PDP and power calculations at three different frequencies and four different voltages were calculated on 90 nm CMOS technology using tanner EDA 13.0v.The proposed Hybrid PTL/CMOS implementation of Vedic multiplier is up to 34.29% power efficient and about 49.82% speedy as compared to the conventional CMOS implementation of array multiplier.