This work demonstrates the design of the digital half adder at the data rate of 1Mbit/s using micro-ring resonators (MRRs). In order to obtain the response of Sum and Carry ports, three micro-ring resonators are used, and a thermo-optic effect is achieved by placing micro heaters on top of each ring. All rings used in the design have identical parameters. Static and dynamic responses of the circuit are provided to show the ability of the device to work properly, and the obtained power level demonstrates that the circuit can transmit data at a specified speed without any additional active elements. The design achieved a compact size of about 658 × 486 µm2.

This work proposes the design of optical SR latch. The fundamental component of the latch is a micro-ring resonator (MRR), which utilizes a plasma dispersion effect with an applied reverse bias voltage to tune its resonance wavelength. The proposed SR latch is made up of two identical micro-ring resonators with similar doped regions and the same logic mode of operation. The memory properties are realized by implementing the feedback loop between the input and output of the circuit. A time-varying simulation is carried out by applying two pseudorandom electrical input signals S and R into the circuit at a data rate of 25 Gbps. The work concludes with a comparative analysis between two optical SR latches (NOR-based and NAND-based).

A high-performance silicon waveguide-based electro-optical 3-to-8 decoder is proposed in this work. Generic 500x220 nm dimensions of the waveguide provide compatibility with other devices and circuits. The length of the active region is 4.5 microns. The n-to-m electro-optical switching circuits utilize both forward and reversed bias NOT gates with a voltage input of -2.5 V and 2.5 V, for logic zero and logic high, respectively. The 3-to-8 decoder showed an input power of the optical signal of 1.26 mW, which is distributed within the circuit, resulting in the maximum output power of approximately 0.3 mW on each of the 8 terminals. 20000 dB/cm mode loss is achieved with a logic input controlled by ±2.5 V. Results show that a data-rate of up to 100 Gbit/s is achieved.

We propose the design of micro-ring resonator-based logic gates. Employment of Silicon-on-insulator (SOI) formation and thermo-optic effect for modulation reduces fabrication cost and complexity. Static and dynamic response spectra are provided.