Digital twin technology evolved initially for production and engineering with Industry 4.0. But now it has entered into various fields like healthcare, aviation, etc. The digital twin models the state of a physical entity or process. The DT continuously predicts the status of defects or failures by closed loop optimization. Due to big data storage capabilities, data fusion algorithms, and artificial intelligence algorithms, DTs are capable of assessing any hidden patterns or unknown correlations, and with self-healing mechanisms, predictive maintenance approach is used to overcome them. In the healthcare applications, DTs of patients and medical devices virtually replicate the patient's physical characteristics or changes in body for correct diagnosis and treatment.

Here the work approaches the detection of fruit maturity level. In addition, a gas sensor is proposed to obtain better sensitivity to know the level of ethylene gas released from matured fruit. Better sensitivity can be achieved by obtaining an enhanced active area, changing the intermediate layer thickness and the pitch value of the electrode. Hexagonal nanostructured zinc oxide is used as a sensing layer. Finally, frequency shift and a total displacement of the device are increased. The hexagonal structured ZnO nanorod-based surface acoustic wave gas sensor may be used to detect ethylene gas in fruit ripening sensor with enhanced sensitivity. This paper reports a simulation of Surface Acoustic Wave (SAW) wave propagation with respect to interdigitated transducer (IDT), piezoelectric material and sensing layers.

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This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

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