SummaryStatic random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

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In this paper, the problem of direction of arrival estimation is addressed by employing Bayesian learning technique in sparse domain. This paper deals with the inference of sparse Bayesian learning (SBL) for both single measurement vector (SMV) and multiple measurement vector (MMV) and its applicability to estimate the arriving signal’s direction at the receiving antenna array; particularly considered to be a uniform linear array. We also derive the hyperparameter updating equations by maximizing the posterior of hyperparameters and exhibit the results for nonzero hyperprior scalars. The results presented in this paper, shows that the resolution and speed of the proposed algorithm is comparatively improved with almost zero failure rate and minimum mean square error of signal’s direction estimate.