-In this paper we discuss the design of a low-voltage (1.5V), continuous-time, biquadratic CMOS filter based on Dynamic Gate Biasing (DGB). We begin by discussing the filter's structure and its tuning mechanism. The filter uses transconductance-C cells and implements low-pass, bandpass and highpass transfer functions. The transconductances are tuned using the gate voltages of MOSFETs operating in the triode region. We review the principle of DGB, and discuss the design of the charge pump based on the filter's performance and tunability requirements. Circuit details of the filter elements and the charge pump are presented along with SPICE simulation results of the overall filter.

A novel approach to design millimeter-wave passive filters is presented using composite right/left-handed (CRLH) structures in a standard CMOS process. The filter is composed of left-handed open split-ring resonators (OSRR) or open complementary split-ring resonators (OCSRR). Such approach leads to a significant reduction in the on-chip area of the filter. It is also straightforward to construct similar filters based on the resonators' equivalent circuit models.

Bandpass sampling is a useful alternative for direct digital downconversion in software radio. It significantly relaxes the analog-to-digital converter (ADC) sampling rate requirement and facilitates the design goal of moving the ADC as close as possible to the antenna. This paper presents a modified interpretation to the graph of allowable sampling frequencies in uniform bandpass sampling. It is shown that the position and guard bands of a downconverted bandpass signal band are highly related to the order of the valid sampling range, called wedge order. An efficient algorithm is then proposed, which significantly reduces the computational load in determining the valid sampling frequencies to downconvert multiple distinct bandpass signals. Conditions for the placement of bandpass signals to utilize a given sampled bandwidth are also discussed.

DC analysis, as a foundation for the simulation of many electronic circuits, is concerned with locating DC operating points. In this paper, a new and efficient algorithm to find all DC operating points is proposed for transistor circuits. The novelty of this DC operating points finder is its twolevel simple implementation based on the affine arithmetic preconditioning and interval contraction method. Compared to traditional methods such as homotopy, this finder offers a dramatically faster way of computing all roots, without sacrificing any accuracy. Explicit numerical examples and comparative analysis are given to demonstrate the feasibility and accuracy of the proposed approach.