Fabrication and Characterization of a Palladium/ Porous Silicon Layer Nicholas LuiA scientific paper can be considered a journey into the logic and mind of the scientist who performed the experiment. This paper, a little unconventional, is written as a reflection of how the author organizes and thinks through his topic. In the telling of it this way, he hopes the journey is as compelling for the reader as it was for him.When porous silicon is plated with a catalytic metal, the two materials can act together as a single entity whose electrical properties are sensitive to its environment -the sensing component of an electrochemical gas sensor. Etching pores into silicon is an electrochemical process; and which type of doped silicon used is one of its key parameters. For nearly all reported porous silicon gas sensors, the silicon has been of the p-doped variety -because pdoped porous etching is better understood and the layers that result from it are more predictable -despite n-doped silicon having potentially significant benefits in ease of fabrication and being more conducive to plating by a catalyst. This experiment is an attempt at creating a palladium plated n-doped porous silicon layer, and an examination into what differentiates this fabrication process and the layers that result from the traditional p-doped type.The porous layers to be plated are to be the same and would ideally have properties that are a close approximation to what a functional gas sensor would require. This experiment defined a process that fabricated this "ideal" layer out of N-type, <100>, double polished silicon wafers with a resistance of 20 Ω cm. The wafers were subjected to the anodic etching method with an HF/ethanol mixture as the electrolyte; and only two (of among many) fabrication parameters were varied: HF concentration of the electrolyte and total etching time. We find that a concentration of 12% HF (by volume) and an etching time of 6 hours result in layers most appropriate to carry into plating. The anodization current density is 15 mA cm -2. Deposition of the catalyst, palladium, is done using the electroless method by immersing the porous layer in a .001M PdCl 2 aqueous bath.Characterization of this Pd/Porous Silicon layer was done by measuring resistivity by four point probe and imaging through Scanning Electron Microscopy. It was found that layers of a v maximum average of 63 ± 6% porosity were created using our fabrication method. There is evidence of palladium deposition, but it is spotty and irregular and is of no improvement despite the n-doping wafer makeup. Resistivity in well-plated regions was measured to be 7-10 Ωcm, while resistivity in regions not well-plated was measured to be 70-140 Ω cm. This is comparable to previous literature values, indicating n-silicon porous silicon can be fabricated and still have potential as a catalytic layer, should metal deposition methods improve.Keywords: Porous Silicon, Electroless Plating, Anodic Etching. vi Chapter 1: IntroductionAt its most general, a porous mate...