Accelerated lifetime testing of five crystalline silicon module designs was carried out according to the Terrestrial Photovoltaic Module Accelerated Test-to-Failure Protocol. This protocol compares the reliability of various module constructions on a quantitative basis. The modules under test are subdivided into three accelerated lifetime testing paths: 85°C/85% relative humidity with system bias, thermal cycling between -40°C and 85°C, and a path that alternates between damp heat and thermal cycling. The most severe stressor is damp heat with system bias applied to simulate the voltages that modules experience when connected in an array. Positive 600 V applied to the active layer with respect to the grounded module frame accelerates corrosion of the silver grid fingers and degrades the silicon nitride antireflective coating on the cells. Dark I-V curve fitting indicates increased series resistance and saturation current around the maximum power point; however, an improvement in junction recombination characteristics is obtained. Severe shunt paths and cell-metallization interface failures are seen developing in the silicon cells as determined by electroluminescence, thermal imaging, and I-V curves in the case of negative 600 V bias applied to the active layer. Ability to withstand electrolytic corrosion, moisture ingress, and ion drift under system voltage bias are differentiated according to module design. The results are discussed in light of relevance to field failures.

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Photovoltaic (PV) modules operate in an extreme environment and are exposed to radiation, humidity, and hot and cold thermal extremes. This paper focuses on polymeric-material degradation during PV-module operation at high ambient temperatures, high solar irradiance and low wind speed. The 2004 version of the IEC 61730 specification requires all polymeric materials used in a photovoltaic module to have a Relative Thermal Index (RTI) or Relative Thermal Endurance Index (RTE) at least 20°C greater than the maximum material temperature measured during the temperature test conducted at 40°C ambient.

Controlled delamination of thin-film photovoltaics (PV) post-growth can reveal interfaces that are critical to device performance yet are poorly understood because of their inaccessibility within the device stack. In this work, we demonstrate a technique to lift off thin-film solar cells from their glass substrates in a clean, reproducible manner by first laminating a polymeric backsheet to the device and then thermally shocking the system at low temperatures (T ≤ −30 °C). To enable clean delamination of diverse thin-film architectures, a theoretical framework is developed and key process control parameters are identified. Focusing on cadmium telluride (CdTe) devices, we show that the lamination temperature and device architecture control the quality of lift-off, while the rate at which the film stack is removed is controlled by the delamination temperature. Crack-free CdTe devices are removed and successfully recontacted, recovering up to 80% of the original device efficiency. The areal density of these devices is ∼0.4 kg m–2, a reduction of over an order of magnitude relative to their initial weight on glass. The framework developed here provides a pathway toward both the development of inexpensive, flexible PV with high specific power and the study of previously buried interfaces in thin-film architectures.

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