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This paper presents an analog decoder computing cell less sensitive to bipolar jnnction transistor (BJT) parasitic elements. Unlike customary cells, the proposed cell does not invert the output probabilities ranking, hence limiting the wrong decoding outcome. This is achieved with a slight complexity increase as only two diodes are added to the basic computing cell. It is also shown that the proposed cell can improve the decoding performance even for large biasing current, opening the way to improve the decoding convergence of an analog BiCMOS decoder. Simulation results are shown for a O.25-p,m BiCMOS process from NXP with minimal size transistors.

This paper analyzes the effect of inherent bipolar transistor parasitic elements on the computing nodes performance used in BJT analog decoders. It is shown that these undesirable effects significantly degrade, up to 85%, the conversion of Log-Likelihood Ratios into probabilities. This can lead to a wrong decoding outcome when complex computing nodes are designed. Simulation results are shown for a 0.25-µm BiCMOS process from NXP.

This paper presents the trade-off between surface, biasing current and performance of an analog turbo decoder. It is shown that the biasing current and the parasitic emitter resistor can deteriorate the performance of a decoder. The parasitic emitter resistor depends on the emitter area and the biasing current depends on the maximum decoding speed required. Simulations show that the parasitic emitter resistor can deteriorate the performance by 0.35dB for BER of 10 −2 for a 0.25-μm process from NXP. It is also shown that an increase of seven percent of the size of the transistor can divide the emitter resistor by four and thus reduces the deterioration of performance to 0.05dB. In the same way, reducing the biasing current improves the performance but reduces the maximum decoding speed.