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Double-gate (DG) MOSFETs came into popularity because of its excellent scalability and better immunity to Short Channel Effects. They are used for CMOS applications beyond the 70 nm node of the SIA roadmaap. However DG devices with channel lengths below 100nm show considerable leakage current and threshold voltage roll off. In this paper, we investigate the influence of channel engineering on the performances of Double Gate (DG) MOSFETs using high-k dielectrics for system-on-chip applications. A Single Halo Double Gate (SH DG) MOSFET is simulated using 2D device simulator and performance is analysed for parameters such as Early voltage, electron velocity and electron mobility. The impact of high-k gate dielectrics on the device short channel performance is studied over a wide range of dielectric permittivity. The device shows 20% increase in drain current as compared to conventional MOSFET. The integration of high-k gate dielectrics further enhances the performance. Drain current increases by 28% and early voltage increases by 34% as the dielectric value increases. The electron velocity also increases with increasing dielectric value.

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