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The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1[Formula: see text]V for the device) gets changed, when various gates in a clock tree are turned ON at different times ([Formula: see text], parameters of the problem) with different values of current ([Formula: see text], other parameters of the problem). Basically, an ensemble of “[Formula: see text]” number of transistors will be turned ON at time [Formula: see text] while it will pump the total current [Formula: see text]. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

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In this paper we will describe a method to determine how to ramp the current linearly inside a silicon chip with respect to every clock period, till it reaches its saturation current. We have assumed a set of transistors switching continuously at a very small time interval κ to have a small saturation current in a time frame much less than one clock period. We continued this process on every clock period with an assumption that more saturation current is drawn by a having more transistors switching during the second clock cycle. This process continues for N number of times for the system to reach the maximum saturation current. We have generated the final current ramp linear in time.  Index Terms-power delivery network, PDN, silicon process speed, rise time, noise in silicon chip, CPU power, dI/dt

Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be -147.001 dBc/Hz and -181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.