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In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multioperand multiply-additions. To reduce the delay time for the multiply-additions, switch circuit is used to change the direct connection between the multipliers and adders, so that the overhead in data transfer is reduced. To change the word-length of the multi-operand multiply-adders, in addition, the switches are also provided in multipliers and adders. By changing to the short wordlength, the numbers of multiplier and adders can be increased. The performance evaluation shows that the delay time for visual feedback control becomes about 6 times faster than that of a parallel processor approach using conventional digital signal processor (DSPs).

This paper describes a design method of high‐speed digital signal processing systems suitable for LSI fabrication. It utilizes the pulse‐train residue arithmetic circuit as a basic building block. This circuit lends itself to parallel and pipeline operations suitable f o r high‐speed digital signal processing, and permits modular‐design of the systems. A new master‐slice LSI on which the pulse‐train residue arithmetic circuits are arranged regularly, is presented. A method of minimizing the chip‐area for NMOS fabrication of the master‐slice is discussed. The layout of the pulse train residue arithmetic circuits on the LSI chip, and several parameters of the master‐slice such as the number of channels are discussed. Some demonstrative examples are presented to show the application of the master‐slice in the design of digital filter. The design method using master‐slices is relatively simple; it minimizes the chip‐count and improves the processing speed.

SUMMARYThe RSA cryptosystem plays an important role in ensuring the security of network communications, although it has the drawback that much time is required for encryption/decryption. This paper presents a high-speed RSA encryption processor employing highly parallel operation based as much as possible in the hardware technology as follows: (1) All of the arithmetic circuits required for encryption/decryption are implemented in the form of redundant binary numbers. (2) Residue calculation is performed by table look-up in a hardware table built in the processor. The table look-up is done in the form of redundant binary numbers. The operation speed of the proposed processor is found to be 60 times that of usual processors when the key length N is 1024 bits. Also, the order of the encryption time of the processor is O (NlogN). The chip size of the processor is estimated as (4.3 × 10 5