An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

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Here we discuss the use of well calibrated resist and etch bias models, in conjunction with a fast microlithographic aerial image simulator, to predict and "optimize" the printed shapes through all critical levels in a dense SRAM design.Our key emphasis here is on "optimization criteria," namely, having achieved good predictability for printability with lithography models, how to use this capability in conjunction with device and circuit design considerations, not just to achieve "best printability," but rather to achieve the combination of best electrical performance, yield, and density. The key lithography/design optimization issues discussed here are: (1) tightening of gate width variation by reducing spatial curvature in the source and drain regions, (2) achieving sufficient contact areas, (3) maximizing process window for overlay, (4) reducing leakage mechanisms by reducing contributions of stress and strain due to the printed shapes of oxide isolation regions, (5) examining topological differences in design during the optimization process, (6) accounting for mask corner rounding, and (7) designing for scaleability to smaller dimensions (here to 0.18 ,um) to achieve optimal design reusability. The last item requires excellent lithography models for examining scaleability issues without hardware.