No abstract

Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (11, 7) and (15, 11) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No. Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.