This paper deals with a new and low cost embedded DRAM (eDRAM) architecture. COLK (Capacitor Over Low K) cell with capacitor placed in the first and thick SiO 2 dielectric has been successfully integrated. 4Mb eDRAM testchip using this new architecture is functional in 45nm node and presents good yield. Moreover we succeed to demonstrate the capability to continue downscaling of eDRAM for nodes down to 32nm and 22nm.

The Z 2-FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

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