This article presents a new concept for electrostatic energy harvesting devices that increase output power under displacement limited inertial mass motion at sufficiently large acceleration amplitudes. The concept is illustrated by two demonstrated electrostatic energy harvesting prototypes in the same die dimension: a reference device with end-stops and an impact device with movable end-stops functioning as slave transducers. Both devices are analyzed and characterized in small and large excitation regimes. We found that significant additional energy from the internal impact force can be harvested by the slave transducer. The impact device gives much higher, up to a factor of 3.7, total output power than the reference device at the same high-acceleration amplitude. The bandwidth of the response to frequency sweeps is beneficially enlarged by up to a factor of 20 by the nonlinear mechanisms of the impact device.

An electrostatic energy harvester with two-stage transduction is investigated for enhancement of bandwidth and dynamic range. The harvester includes a primary proof mass with two main transducers and end-stops for the proof mass functioning as secondary transducers. In the small acceleration regime, the power is primarily obtained from the main transducers. In the high acceleration regime, the mass impacts the end-stops and actuates the secondary transducers, generating additional output power. The device is designed and fabricated using the SOIMUMPs process and has a total active area of 4 × 5 mm 2 . Under wideband acceleration at high levels, the experimental results show that the total output power increases to about twice the output power of the main transducers, while the 3 dB-bandwidth is enlarged by a factor of 6.7 compared to the linear-response bandwidth at low levels. In comparison with a reference device made with the same die dimensions, the two-stage device improves output power instead of saturating when the maximum mass displacements of both devices reach the same limit. Measurement of output power demonstrates that the device with the transducing end-stops give an efficiency of 23.6%, while this value is 14.1% for the reference device with the conventional end-stops, at an acceleration spectral density of S a = 19.2 × 10 −3 g 2 Hz −1 . The efficiency is improved about by 9.5% in the impact regime.

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This paper investigates in detail a micro scale in-plane gap closing electrostatic energy harvester with strong nonlinearities in squeeze-film damping, electromechanical coupling, and impacts on end-stops. The device shows softening response on increasing the bias voltage and saturation behavior on impact with end-stops at high enough acceleration amplitude. We demonstrate that a lumped model can adequately describe the measured nonlinear behavior for a range of operating conditions with nonlinear fluid damping force and impact force included in the model. While modeling capacitances, a finite-element method (FEM) is used to analyze fringing field effects on the capacitance variation for gap closing electrodes. The nominal capacitance is obtained from FEM analysis, for a range of under-cut values in the fabrication process treated as a free parameter in the model. The device modeled for linear and nonlinear squeeze-film damping force highlights the importance of nonlinear damping force to understand the device behavior over the range of operating conditions. With the compliant end-stops treated as spring-dampers and with proper choice of end-stop damping-coefficient, the model successfully captures the end-stop nonlinearities for a particular operating point and reproduces the dynamic pull-in phenomena at 8 V bias, and rms acceleration 0.6 g, as observed in the experiments. Thus, the model described in this paper reproduces the subtle nonlinear effects dominating the dynamics of an in-plane gap closing electrostatic energy harvester.[ 2015-0107]Index Terms-Electrostatic devices, energy harvester, nonlinear systems, vibrations. 1057-7157

Abstraet:This work deals with off-boding some ,time critical parts in the process of performing intrusion detection from sofmare to reconfigurable hardware (FPGA). Signatures of known attacks must typically be compared io high speed network traffic, and sir@ matching becomes a bottleneck Content Addressable Memories (CAMS) are known to be fast string matchers, but offer little flexibility. For that purpose a Variable Word-Width CAM for fast shirzg matching has been designed and implemented in an FPGA A typical feature for thk CAM is that the length of each word is independent from the others, in contrast to common CAMs where all worak have the same length,The design has been functionally tested on a development board for a CAM of size 1822 bytes (128 words). This design processes 8 bits per clock cycle and has a reported maximum clock speed of 100 MHL This gives a thoughput of 800 Mbit/s IntroductionThe speed of todays networks is of such a kind that a general purpose CPU must struggle to process the network data. The CPU must also have resources left for other application processes. The amount of processing required on network data is increasing due to the need for intrusion detection, cryptographic processing and more [I].One way to free the CPU from heavy tasks is to convert some of the software or parts of a given software, into hardware. In this work a part of an Intrusion Detection System (IDS), Snort [Z], the string matcher will be implemented in hardware.As time goes by, we can expect that new pattems will be discovered and a reconfiguration of the hardware will then be required. For resemh purposes it is expected that pattems will change frequently, and that they are of different sizes. A suited hardware technology is Field Programmable Gate Arrays (FPGA) which is easily reconfigured to accommodate these changes.The main contribution of this paper is to implement a Variable Word-Width Content Addressable Memory (CAM) in FPGA for string matching. Thereby great flexibility is obtained with respect to how the Snort rule set is defmed.In order to design a system for an FPGA, a Hardware Description Language (HDL) is needed. VHDL was chosen for this work in spite of its somewhat restricted programming features. The main reason for this is that VHDL is well known at the University of Oslo. One result from this work is that it is now possible to describe the actual CAM design in VHDL by taking advantage of all programming abilities that are common to any programming language. Thereby reconfigurability of the CAM has been made a simple task.The CAM is implemented in hardware by using Xlinx ISE 6.1.03i. With this tool various reports are generated These reports were be used for giving estimates of how much of the resources of an FPGA will be used by each specific design and the speed obtained.Section 2 gives an overview ofIDS, whereas the CAM design is described in section 3. The results are summarized in section 4 and the conclusion is given in section 5. 2. Intrusion Detection Systems o s )It tums out that there...