ABSTRACT:A new very large scale integration (VLSI) algorithm for a 2 -length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. In the proposed method multiply the multipliers by using array multiplier and to add the co-efficients by using Carry Look-ahead Adder (CLA). In the proposed system we are reducing the area by using the array multiplier and Carry Look-ahead Adder (CLA). The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the sub expression sharing techniques that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI. KEYWORDS:Discrete Hartley transform (DHT), DHT domain processing, fast algorithms. I. INTRODUCTIONThe Discrete Fourier transform (DFT) is used in many digital signal processing applications as in signal and image compression techniques, filter banks [1], signal representation, or harmonic analysis [2]. The discrete Hartley transform (DHT) [2], [3] can be used to efficiently replace the DFT when the input sequence is real. In the literature, there are some fast algorithms for the computation of and some algorithms for the computation of generalized DHT [8]- [10]. There are also several split-radix algorithms for computing DHT with a low arithmetic cost. Thus, Sorensen et al. [11] and Malvar [12] proposed split-radix algorithms for DHT with a low arithmetic cost. Bi [13] proposed another split-radix algorithm where the odd-indexed transform outputs are computed using an indirect method. The classical split-radix algorithm is difficult to implement on VLSI due to its irregular computational structure and due to the fact that the butterflies significantly differ from stage to stage. Thus, it is necessary to derive new such algorithms that are suited for a parallel VLSI system. There are also in the literature several fast algorithms that use a recursive strategy as those in [14] for discrete cosine transform (DCT) and that in [10] for generalized DHT. Since DHT is computationally intensive, it is necessary to derive dedicated hardware implementations using the VLSI technology. One category of VLSI implementations is represented by systolic arrays. There are many systolic array implementations of . Systolic array architectures are modular and regular, but they use particularly pipelining and not parallel processing to obtain a highspeed processing. In the literature, highly parallel solutions as those in [8] and [19] were also proposed. In [8], a highly parallel and modu...