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A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. The design was implemented in both bit-parallel and bit-serial architectures and a comparison of design tradeoffs using various measures is presented. On an Xilinx Virtex XCV300-6 FPGA, the bit-parallel implementation delivers an encryption rate of 1166 Mb/sec at a 82 MHz system clock rate, whereas the bit-serial implementation offers a 600 Mb/sec throughput at 150 MHz. Both designs are suitable for real-time applications, such as on-line high-speed networks. The implementation is runtime reconfigurable such that key-scheduling is done by directly modifying the bitstream downloaded to the FPGA, hence enabling an implementation without the logic required for key-scheduling. Both implementations are scalable such that higher throughput is obtained with increased resource requirements. The estimated performances of the bit-parallel and bitserial implementations on an XCV1000-6 device are 5.25 Gb/sec and 2.40 Gb/sec respectively.

Virtunl Private Networks (VPN) are becoming increasingly populor network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore. certain security measures must be used to deal with these privacy issues. The Internet Protocol Security (IPSec) by the Internet Engineering Task Forre (IETF) addresses the abovementioned security issues and the Free Secure Wide Area Network (FreeS/WAN) is an open source software implementation of IPSec for Linvz which uses thple-DES as the default encryption mode.As shown in this paper, the perfonnance of FreeS/WAN with IPSec is 50% ofthat without encryption. In order to improve its performance, a field programmable gate array (FPGA) based triple-DES accelerator was built on a reconfigurable computing development platfonn called Pilchard and achieved a throughput of more than 120 Mb/sec for triple-DES in cipherblock chaining mode, a speedup of 3 over a software implementation. Measurements show that an FPGAaccelerated FreeS/WAN offers a 30% speedup for the TCP protocol over the original software library.

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