-The Global Positioning System (GPS) satellites transfer accurate time from atomic clocks, thus enabling the receivers on Earth to produce high-stability synchronization signals (i.e., trains of low-jitter pulses without drift). The timing accuracy of the generated stream of pulses depends on the features as well as on the cost of the specific GPS receiver employed. This paper describes a fully digital synchronization circuit that is able to reduce the jitter associated to the 1 pulse per second (1-pps) signal generated by a typical low-cost receiver of moderate timing accuracy within a short settling time interval. The proposed circuit has been implemented using an FPGA and the jitter reduction has been estimated experimentally.

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Future Internet traffic will be dominated by ondemand streaming media flows, such as IPTV, 3D/HD video, gaming, virtual reality, and

In order to achieve ultra scalable IP packet switching it is essential to minimize "stopping" of the serial bit streams. In our recent experimental work we demonstrated how this can be achieved with an ultra-scalable switching architecture reaching multi-terabits per second (10-100 Tb/s) in a single chassis. The implemented testbed uses only off-the-shelf optical and electronic components. The scalability of this architecture is the direct outcome of how global time (i.e., UTC -coordinated universal time) and pipeline forwarding are utilized. The paper presents the design of a prototype switch and experimental activity with it.

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