International audienceRFID ICs such as EPC Class 1 GEN2 tag are low cost tags which are in some cases used for critical or secure applications. Increasing their robustness is not trivial due to the wide range of error sinks (EM perturbations, attacks...). Moreover increasing the robustness must have a minimum impact on the die area but also must fit with a standardized protocol. In this work we propose a design methodology in order to develop hardened digital tag architecture with a dedicated verification environment taking into account all RFID system parameter

International audienceIn this paper, we propose a new RFID tag monitoring approach, based on adding an infrastructure circuit to simultaneously monitor and save faulty tag behaviour, in order to enable the implementation of advanced RFID diagnosis functions and mainly to reinforce tag security against fault attacks. The added infrastructure circuit is essentially composed of hardware assertions exclusively devoted to on-line fault detection on the tag. Saved information about detected faults can then be read using RFID readers. Our approach is initially evaluated and implemented in a developed tag emulator platform based on an FPGA board, then thoroughly exercised to demonstrate its valuable contribution to diagnosis means. Experimental results, obtained via random fault injection mechanism, show the effectiveness of the proposed approach

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