In this work, we propose fully integrated multilayer stacked topology of asymmetrical inductor with patterned ground shield (PGS), which also serves as capacitor. The main aim of the study is efficient usage of limited chip area for integrated passive components by challenging layout properties of asymmetrical integrated inductor and integrated MOS capacitor and enhancing their main electrical properties. Several principles of geometry modifications(vertical and horizontal parallelization, slicing, tapering, equal path lengths) were applied to a four-turn octagonal asymmetrical integrated inductor with the series DC resistance RL = 1.75 Ω and inductance L = 11.66 nH on low frequencies. Remaining area under integrated inductor was used for a capacitor with capacitance CP GS = 1.6 nF and the equivalent series resistance RC = 7.25 Ω. The whole structure was designed in a standard 65nm CMOS technology for use in a switched DC-DC power converter working in MHz-range for a Photovoltaic (PV) Energy Harvester (EH).

In this paper, an investigation of the efficiency of fully on-chip DC-DC step-up converter realized in a standard 130 nm CMOS technology is presented. The converter has been designed for regulated output voltage of 1.2 V with an on-chip inductor and an output capacitor. The obtained results show that the proposed on-chip converter can achieve the efficiency up to 98 % and the output power up to 6 mW. The performed analysis investigates possibilities for the further improvement focused on the maximum efficiency and output power.

This paper presents the efficiency investigation of a fully on-chip DC-DC step-up converter realized in a standard 130 nm CMOS technology and its comparison to previous works. Research is mainly focused on finding the optimum operation point to provide the high output power and conversion efficiency of the on-chip converter solution. The obtained output voltage of 1.2 V shows 98.6 % efficiency of power conversion, and the maximum output power of 6 mW is achieved. Another performed analysis has been focused on impact of inductor properties as well as impact of the control circuit on the main parameters of the developed boost voltage converter.

This paper presents an overview and State-of-the-Art of fully integrated inductors with common fabrication processes used for implementation of these structures into a chip. The first step is an overview of fabrication technologies that starts with standard CMOS general purpose processes expanded by Far-BEOL and substrate alteration process (SOI, Silicon Embedded, TSV, TGV, PTH, Core Insertion); and continues to advanced process nodes like SMMT and Bond Wire utilization. Then, an overview of fully integrated inductor structures consists of selected topologies with notable parameters achieved in last few years. Critical parameters of integrated inductors include: inductance L DC , inductance density L A , quality factor Q, selfresonant frequency FSR and series resistance R DC . These parameters are as important as the purpose and fabrication process.