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Flash memory has become one of the most important segments of the semiconductor industry in recent years. Flash memory is also an important driver of the lithography roadmap, with its dramatic acceleration in dimensional shrink, pushing for ever smaller feature sizes. The introduction of the XT:1700Fi and XT:1900Gi have brought the 45nm node and below within reach for memory makers. At these feature sizes mask topology and the material properties of the film stack on the mask play an important role on imaging performance. Furthermore, the break up of the array pitch regularity in the NAND-type flash memory cell by two thick wordlines and a central space, leads to feature-center placement (overlay) errors, that are inherent to the design. An integral optimization approach is needed to mitigate these effects and to control both the CD and placement errors tightly.In this paper we will present the results of aerial image measurements on mask level of a NAND-Flash Memory Gate layer using AIMS TM 45-193i. Various imaging relevant parameters, such as MEEF, EL, DoF and placement errors are measured for different mask absorber materials for features sizes ranging from 39nm half pitch to 41nm half pitch design rule on wafer level. The AIMS TM measurements are compared to experimental results obtained with a XT:1900Gi hyper-NA immersion system. Mask optimization strategies are sought to increase Depth of Focus and minimize feature-center placement errors.

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